IDDT Testing versus IDDQ Testing

Authors:
Yinghua Min;Zhongcheng Li
Affiliations:
Center for Fault-Tolerant Computing, CAD Lab., Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China 100080. E-mail: min@mimi.cnc.ac.cn;Center for Fault-Tolerant Computing, CAD Lab., Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China 100080.
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
1998

Citing 4
Cited 7

Transient power supply current monitoring—a new test method for CMOS VLSI circuits

Journal of Electronic Testing: Theory and Applications
Transient Power Supply Current Testing of Digital CMOS Circuits

Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Waveform Polynomial Manipulation Using Bdds

ATS '96 Proceedings of the 5th Asian Test Symposium
Monitoring power dissipation for fault detection

VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium

Experimental Results on BIC Sensors for Transient Current Testing

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Dynamic Power Supply Current Testing of CMOS SRAMs

Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
CMOS open defect detection by supply current test

Proceedings of the conference on Design, automation and test in Europe
IDDT: fundamentals and test generation

Journal of Computer Science and Technology
Transient Current Testing of 0.25 µm CMOS Devices

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Scaling of iDDT Test Methods for Random Logic Circuits

Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Quantified Score

Hi-index	0.01

Visualization

Abstract

IDDQ testing has progressed to become a worldwide accepted test method to detect CMOS IC defects.However, it is noticed that observing theaverage transient current can lead to improvements in real defectcoverage, which is referred to IDDT testing. This letter presents a formal procedure to identifyIDDT testable faults, and togenerate input vector pairs to detect the faults based on Boolean process.It is interesting to note that those faults may notbe detected by IDDQ or other test methods, which shows the significance of IDDT testing.