A Novel Delay Fault Testing Methodology Using On-Chip Low-Overhead Delay Measurement Hardware at Strategic Probe Points

  • Authors:

  • A. Raychowdhury;S. Ghosh;S. Bhunia;D. Ghosh;K. Roy

  • Affiliations:

  • Purdue University;Purdue University;Purdue University;Purdue University;Purdue University

  • Venue:
  • ETS '05 Proceedings of the 10th IEEE European Symposium on Test
  • Year:
  • 2005

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Abstract

We propose a delay fault testing methodology using on-chip delay measurement hardware. We have designed a process-tolerant, low-overhead delay measurement hardware and developed an algorithm to judiciously insert the hardware at internal nodes of logic blocks. Experimental results for a set of ISCAS89 benchmarks show up to 16.9% improvement in transition fault coverage and up to 10.5% increase in the number of detected faults for segment delay fault model, with fixed test length. The reduction in test length is up to 59% for transition fault, with fixed target coverage. The delay and area overhead due to additional DFT logic is limited to 2% and 4% respectively.