Transistor sizing for reliable domino logic design in dual threshold voltage technologies

Authors:
Seong-Ook Jung;Ki-Wook Kim;Sung-Mo Steve Kang
Affiliations:
Coordinated Science, Laboratory, ECE Department, University of Illinois at Urbana-Champaign;Pluris, Inc., 10455 Bandley Dr., Cupertino, CA;Dean of Baskin School of engineering, University of California at Santa Cruz
Venue:
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Year:
2001

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Abstract