Synthesis of Dual-VT Dynamic CMOS Circuits

  • Authors:
  • Debasis Samanta;Ajit Pal

  • Affiliations:
  • -;-

  • Venue:
  • VLSID '03 Proceedings of the 16th International Conference on VLSI Design
  • Year:
  • 2003

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Abstract

Main source of power dissipation for dynamic CMOS circuits isdue to charging and discharging of intrinsic capacitances,commonly referred to as switching power. As switching powerdissipation is proportional to the square of supply voltage,lowering the supply voltage is the most effective way to reduceswitching power dissipation. However, the reduction ofswitching power by lowering the supply voltage takes place atthe cost of performance. In order to maintain the performance,it is necessary to scale down the threshold voltage. But, as thethreshold voltage is scaled down, the subthreshold leakagecurrent increases dramatically leading to large increase inleakage power dissipation. Recent research has revealed thatwith the gradual shrinking of device sizes, the leakage powerdissipation is becoming more and more dominant, and it islikely to become comparable to switching power dissipation infuture generation VLSI circuits. This has motivated us todevelop suitable technique for the reduction of leakage powerdissipation in dynamic CMOS circuits, a problem, which has notbeen addressed by any researcher. This paper proposes atechnique for containing the leakage power using two thresholdvoltages (dual-VT) in the realization of circuits. Necessary carehas been taken such that the dual-VT dynamic circuits can bekept in standby mode and dissipates small leakage power.Substantial reduction in leakage power has been demonstratedwithout compromise in performance for both domino and norastyle of realizations.