Domino logic synthesis using complex static gates
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Technology mapping for domino logic
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Synthesis of Dual-VT Dynamic CMOS Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
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This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, conventional logic design approaches cannot be used for Domino/Nora logic synthesis.To over come this problem, we have used a new concept called unate decomposition of Boolean functions. The unate decomposition expresses a general Boolean function in terms of a minimum number of positive and negative unate functions, which can be readily mapped to a two-level network of Domino/Nora logic circuit. To deal with functions of very large number of variables, a function is first decomposed into sub-functions of not more than 15 variables. Unate decomposition is efficiently performed for each of these sub-functions independently. However, two-level Domino/Nora realization for these functions are quite often not suitable for the realization of practical VLSI circuits having reasonable delay, because of the large number of series/parallel MOS transistors. To over come this limitation, we have performed multilevel decomposition of each sub-function.The netlist produced by the multilevel decomposition directly maps (on-the-fly) to Domino/Nora cells.In order to analyze the circuits synthesized by our approach, we have estimated the delay and power of the circuits based on the models presented in the paper. Our result is then compared with the static CMOS circuits synthesized by standard SIS tool. Our approach has been found to achieve better results with regard to area, delay and power consumption compared to the existing approaches. It is envisaged that the synthesized Domino/Nora circuits will be suitable for realizing high-performance and low power circuits.