Static timing analysis for self resetting circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Domino logic synthesis using complex static gates
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
High speed CMOS design styles
Towards Synthesis of Monotonic Asynchronous Circuits from Signal Transition Graphs
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
Wave pipelining using self reset logic
VLSI Design
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A new family of self-reset logic (SRL) cells is presented in this paper. The single-ended basic structure proposed realizes an incomplete logic family, since it is incapable of inverting logic. Thus, a dual-rail SRL (DRSRL) implementation is also proposed. These cells maintain small delay variations for all input combinations, once minimum timing requirements on inputs are satisfied, and produce output pulses of fairly constant width for varying fanout, leaving enough headroom in the design to accommodate process, supply voltage, and temperature variations. These properties simplify the implementation of datapath and control circuits where the logic depth does not affect the stage output pulse width, eliminating the need for pulse-width controlling circuits required in previous works on SRL. In SRL, power is consumed only if new data are pumped through the logic. The clock grid is limited to the registers that launch and receive the signal path. The clocking overhead is thus reduced, compared with other dynamic designs, and it is especially suitable for wave pipelining. Case study examples and simulated characterization data are included to show the design methodology.