High speed CMOS design styles
Hierarchical physical design methodology for multi-million gate chips
Proceedings of the 2001 international symposium on Physical design
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A design methodology for the implementation of multi-million gate system-on-chip designs is described. The new methodology is based on the creation of a silicon virtual prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the 'cockpit' where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The silicon virtual prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.