Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
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Skin effects should be considered for accurate deep-submicron (DSM, 0.35mm and below) interconnect modeling [1][2][3]. Conventionally the sheet-r for uniform or plasma-etched conductors is reasonably constant, so the frequency-dependent skin effect can be found by straightforward field simulations, which require sheet-r being constant [4][5][6]. In that case, the skin-depth is primarily function of harmonic frequency and the environment. However, for damascene-processed conductors, the sheet-r is function of line width [7]. Therefore, the impedance (resistance and inductance in this paper) has to be determined by field solvers using a new methodology we propose in this paper: For each DSM technology, sets of interconnect structures with comprehensive range of line widths and neighbors for each metal level are provided and simulated in advance. In this way, a library for each DSM technology is available for accurate and efficient VLSI interconnect modeling. Future work is provided at the end of this paper.