Matrix computations (3rd ed.)
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient inductance extraction via windowing
Proceedings of the conference on Design, automation and test in Europe
Inductance 101: modeling and extraction
Proceedings of the 38th annual Design Automation Conference
On the efficacy of simplified 2D on-chip inductance models
Proceedings of the 39th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Transmission line design of clock trees
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Equipotential shells for efficient inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
INDUCTWISE: inductance-wise interconnect simulator and extractor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The present work is centered in the controversy between two approaches to inductance extraction: loop vs. partial treatments for IC applications. We advocate for the first one, justifying this claim in terms of representing more realistically the physical situation, as well as having better sparseness properties. We argue that the drawbacks of loop inductance treatment are small for frequencies above 1 GHz. Within the loop inductance formulation, we develop an efficient way of calculating mutual inductances between loops in terms of the field generated by a magnetic dipole. On numerical simulations, the dipole approximation shows good accuracy when compared to FastHenry, down to distances of 30μ for 0.13μ processes. The dipole approximation leads naturally to selection rules for discarding certain couplings that can be experimentally verified.