Evaluating carbon nanotube global interconnects for chip multiprocessor applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we develop a quantitative design technique for multi-walled carbon nanotube (MWCNT) based interconnect, which we utilize to examine the performance and reliability of future nanotube-based interconnect solutions. Leveraging an analytical RLC model for MWCNTs, we create the first closed-form formulation for the optimal nanotube diameter and nanotube bundle height. The results indicate that the proposed design method decreases delay by 21% and 29% on average compared to non-optimized MWCNTs and single-walled carbon nanotube (SWCNT) bundles. We also find that large diameter MWCNT bundles are significantly more susceptible to process variations than SWCNT bundles, which will have important reliability implications in future nano-scale ICs.