An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Implementing Asynchronous Circuits on LUT Based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
An Asynchronous Dataflow FPGA Architecture
IEEE Transactions on Computers
FPGA Architecture for Multi-Style Asynchronous Logic
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A High-Performance Asynchronous FPGA: Test Results
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Rapid Prototyping of a Self-Timed ALU with FPGAs
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
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This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full adders and ripple carry adders, as well as self-timed ring based applications. The comparison analysis has been carried out by prototyping the circuits on standard programmable logic devices, and using the development tools provided by vendors. Although the feasibility of asynchronous circuits has been demonstrated in such devices, the experimental results clearly show the inefficiency of such a kind of digital system implementation. This is mainly due to the architecture characteristics of the programmable devices and the logic synthesis realized by the development environments. Remarks and suggestions are derived from this study for a new FPGA architecture devoted to asynchronous design.