An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

Authors:
Yoshiya Komatsu;Shota Ishihara;Masanori Hariyama;Michitaka Kameyama
Affiliations:
Tohoku University, Miyagi, Japan;Tohoku University, Miyagi, Japan;Tohoku University, Miyagi, Japan;Tohoku University, Miyagi, Japan
Venue:
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Year:
2011

Citing 2
Cited 0

An Asynchronous Dataflow FPGA Architecture

IEEE Transactions on Computers
Principles of Asynchronous Circuit Design: A Systems Perspective

Principles of Asynchronous Circuit Design: A Systems Perspective

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Abstract

This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous FPGA, the power consumption is reduced by 38% for the workload of 15%.