Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
SMT Layout Overhead and Scalability
IEEE Transactions on Parallel and Distributed Systems
Imagine: Media Processing with Streams
IEEE Micro
Compiler managed micro-cache bypassing for high performance EPIC processors
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Dynamic addressing memory arrays with physical locality
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A quantitative analysis of the speedup factors of FPGAs over processors
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
An Asynchronous Dataflow FPGA Architecture
IEEE Transactions on Computers
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In this paper, we propose a new load-distribution processor model that adapts hardware resources optimally and autonomously to target applications on dynamical reconfiguration devices. In the procedure of load-distribution, the processor detects the load of task-processing by itself and changes the kinds and number of resources optimally. We adopt the master-slave model, which consists of a management unit (master) and two or more processing units (slaves). The former detects overload and distributes tasks and the latter execute task-processing. One of the features of this model is that it is possible to change the number of processing units without reconfiguring the management unit's structure. Moreover, in order to use this load-distribution system efficiently, we propose a reordering unit that buffers data from processing units and outputs rearranged data. In this paper, we describe the requirements and organization of a management unit and processing units. Next, we implement the proposed model on real chips of PCA, a dynamical reconfiguration device, and measure the overheads of processing and reconfiguration. Finally, we evaluate the proposed model based on the experimental results. From the experiments, we show that our proposed model can reduce a designer's efforts to estimate the amount of hardware resources according to applications in advance.