Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Slack Elasticity in Concurrent Computing
MPC '98 Proceedings of the Mathematics of Program Construction
An Asynchronous Dataflow FPGA Architecture
IEEE Transactions on Computers
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Design of a reconfigurable pulsed quad-cell for cellular-automata-based conformal computing
International Journal of Reconfigurable Computing
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We present a new method for implementing asynchronous FPGA logic cells which are configurable at pipeline level. Previous implementations of the basic elements of these logic cells were based on the pre-charged logic implementation which imposes some limitations on the size of the logic cell due to the stacking problem. To overcome this limitation we propose a novel method for implementing these templates. Our method uses standard single-rail computational circuits. It does not have any stacking problem and is not limited in size. The results show that a 4-input logic cell implemented by this method outperforms a previous 3-input logic cell by 16% in speed and 29% in power with a negligible area overhead.