Asynchronous realization of algebraic integer-based 2D DCT using achronix speedster SPD60 FPGA

Authors:
Nilanka Rajapaksha;Amila Edirisuriya;Arjuna Madanayake;Renato J. Cintra;Dennis Onen;Ihab Amer;Vassil S. Dimitrov
Affiliations:
Electrical and Computer Engineering, Auburn Science and Engineering Center, The University of Akron, Akron, OH;Electrical and Computer Engineering, Auburn Science and Engineering Center, The University of Akron, Akron, OH;Electrical and Computer Engineering, Auburn Science and Engineering Center, The University of Akron, Akron, OH;Department of Statistics, Federal University of Pernambuco, Recife, PE, Brazil;Department of Electrical and Computer Engineering, ICT 402, Schulich School of Engineering, University of Calgary, Calgary, AB, Canada;Advanced Micro Devices, Markham, ON, Canada;Department of Electrical and Computer Engineering, ICT 402, Schulich School of Engineering, University of Calgary, Calgary, AB, Canada
Venue:
Journal of Control Science and Engineering - Special issue on Hardware Implementation of Digital Signal Processing Algorithms
Year:
2013

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Abstract

Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltagetemperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transformcoefficients having error within 1%. The performance of the 65 nmasynchronous hardware in terms of speed of operation is investigated and compared with the 65 nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy improvements obtained.