Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Checking Delay-Insensitivity: 104 Gates and Beyond
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Development of a large word-width high-speed asynchronous multiply and accumulate unit
Integration, the VLSI Journal
Automated energy calculation and estimation for delay-insensitive digital circuits
Microelectronics Journal
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A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, commonly referred to as the NULL cycle. The NCR technique exploits parallelism by partitioning input wavefronts, such that one circuit processes a DATA wavefront, while its duplicate processes a NULL wavefront. A NCR architecture is developed for both dual-rail and quad-rail circuits, using either full-word or bit-wise completion. To illustrate the technique, NCR is applied to case studies of a dual-rail nonpipelined 4-bit × 4-bit unsigned multiplier using full-word completion, a dual-rail optimally-pipelined 4-bit × 4-bit unsigned multiplier using full-word completion, and a dual-rail optimally-pipelined 4-bit × 4-bit unsigned multiplier using bitwise completion. The application of NCR yields a speedup of 1.57, 1.55, and 1.34, respectively, over the standalone versions, while maintaining delay-insensitivity. Furthermore, NCR is applied to a single slow stage of two pipelined designs to boost the pipelines' overall throughput by 20% and 26%, respectively.