Communications of the ACM
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A new polynomial-time algorithm for linear programming
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
AMULET3: A High-Performance Self-Timed ARM Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
The best of both worlds: the efficient asynchronous implementation of synchronous specifications
Proceedings of the 41st annual Design Automation Conference
Cycle period analysis and optimization of timed circuits
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
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De-synchronous is a very useful method to design asynchronous circuit automatically from synchronous description of circuits. This paper introduces an optimal design method based on Control Graph which is an abstract model of the de-synchronous circuit. The main purpose of this optimal design method is to reduce the extra overhead in the area of the de-synchronous circuit. The optimization algorithm takes the performance evaluation function based on the Control Graph of the de-synchronous circuit as its heuristic function. The performance evaluation function presented in this paper is a linear programming problem. In the end of this paper, the optimal method is applied to a set of benchmark circuits. The number of the local controllers in these circuits is markedly reduced by 54%, and the number of C-elements that is required to construct the handshake circuitry between local controllers is also reduced by 76.3%. So the entire area of the circuit is sharply reduced. Because this design method is directed by the performance evaluation function of the circuit, there is no penalty in performance of the de-synchronous circuit.