Cycle period analysis and optimization of timed circuits

Authors:
Lei Wang;Zhi-ying Wang;Kui Dai
Affiliations:
School of Computer, National University of Defense Technology, Changsha, Hunan province, China;School of Computer, National University of Defense Technology, Changsha, Hunan province, China;School of Computer, National University of Defense Technology, Changsha, Hunan province, China
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Abstract

In this paper, a method is proposed to analyze the minimum average cycle period of the timed circuits. Timed Petri net is used to model timed circuits. Our method is focus on structural analysis of the Petri net model of the timed circuits, which is another way to reduce the state space of the analyzed model. Then an algorithm is proposed to optimize the performance of timed circuit by asynchronous retiming technique. The algorithm balances the asynchronous pipelines to gain the target cycle period while minimize the area at the same time. Experimental results demonstrate the computational feasibility and effectiveness of both approaches.