Canonical Prefixes of Petri Net Unfoldings
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
ILP Models for the Synthesis of Asynchronous Control Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
On the Complexity of Consistency and Complete State Coding for Signal Transition Graphs
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
On the Complexity of Consistency and Complete State Coding for Signal Transition Graphs
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
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The paper presents a new method for checking Uniqueand Complete State Coding, the crucial conditions in thesynthesis of asynchronous control circuits from Signal TransitionGraphs (STGs). The method detects state coding conflictsin an STG using its partial order semantics (unfoldingprefix) and an integer programming technique. This leads tohuge memory savings compared to methods based on reachabilitygraphs, and also to significant speedups in manycases. In addition, the method produces execution pathsleading to an encoding conflict. Finally, the approach is extendedto checking the normalcy property of STGs, which isa necessary condition for their implementability using gateswhose characteristic functions are monotonic.