An efficient critical race-free state assignment technique for asynchronous finite state machines
DAC '93 Proceedings of the 30th international Design Automation Conference
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Modulo-N Counters: Design and Analysis of Delay-Insensitive Circuits
Proceedings of the Second IFIP WG10.2/WG10.5 Workshop on Designing Correct Circuits
VLSI Programming of a Modulo-N Counter with Constant Response Time and Constant Power
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Formal Asynchronous Systems Modelling
Fundamenta Informaticae
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A procedure of designing a self-timed device defined by the model of finite automaton is suggested. In accordance with the chosen automaton standard implementation structure from the automaton transition/output graph one derives the Signal Graph Specification that then is processed by the formal synthesis procedure for self-timed implementation. The design procedure is illustrated by two examples: Stack Memory and Counter with Constant Acknowledge Delay.