ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Relative Timing Based Verification of Timed Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Asynchronous Nano-Electronics: Preliminary Investigation
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
A study of asynchronous design methodology for robust CMOS-nano hybrid system design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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Nano crossbar architectures are based on emerging nan- otechnology fabricated using self-assembly processes to reduce manufacturing costs and achieve higher levels of integration. An extreme parameter variation due to nondeterministic nanofabrication is one of the major challenges in this nanotechnology. Asynchronous circuits seem a promising option for logic implementation on nano-crossbar architectures. However, the circuit must be designed in such a way to guarantee the required timing constraints, under extreme delay variations, to ensure correct functionality. In this paper, we propose an efficient implementation of Quasi Delay Insensitive (QDI) asynchronous circuits on nano crossbar arrays. The proposed method guarantees timing requirements in isochronic forks with respect to worst case delay variations. Extensive Monte Carlo simulations for delay variations on a set of representative designs confirm that our approach can tolerate 200% delay variations with success rate of 99.55%, compared to only 0.13% achieved by the previous work, with almost 100% area overhead.