An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design

Authors:
W. Kuang;J. S. Yuan
Affiliations:
-;-
Venue:
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Year:
2003

Citing 4
Cited 0

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Abstract

This paper combines an adaptive supply-voltagescheme with self-timed CMOS digital design, to achievelow power performance. The supply-voltageautomatically tracks the input data rate of the data pathso that the supply-voltage can be kept as small aspossible while maintaining the speed requirement. Thisadaptive supply-voltage scheme employs the handshakesignals directly to detect the speed of data path withoutusing FIFO buffer. This leads to a very simple logiccontrol whose power loss is negligible. Cadence SPICEsimulation shows the effectiveness of this scheme for lowpower applications based on 0.18 µm CMOS process.