Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits

Authors:
Yutaka Deguchi;Nagisa Ishiura;Shuzo Yajima
Affiliations:
Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan;Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan;Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan
Venue:
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Year:
1991

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Abstract