Precise timing verification of logic circuits under combined delay model

Authors:
Shinji Kimura;Shigemi Kashima;Hiromasa Haneda
Affiliations:
Dept. of Electronics Engineering, Kobe University, 1-1 Rokkodai, Nada, Kobe, 657 Japan;Dept. of Electronics Engineering, Kobe University, 1-1 Rokkodai, Nada, Kobe, 657 Japan;Dept. of Electronics Engineering, Kobe University, 1-1 Rokkodai, Nada, Kobe, 657 Japan
Venue:
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Year:
1992

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