Keynote speech: testing methodologies for embedded systems and systems-on-chip
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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Abstract: In this paper, we describe a high-level test synthesis algorithm for operation scheduling and data path allocation. It generates highly self-testable data path design while maximizing the sharing of test registers, which means only a small number of registers is modified for BIST. The algorithm also produces design with high test concurrency, thereby decreasing test time. In our approach, module allocation is guided by a testability balance technique. Register allocation is achieved by an incremental sharing measurement which chooses allocation steps that result in large increases in the sharing degrees of registers. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.