Algorithms for High-Level Synthesis
IEEE Design & Test
Cone Based Clustering for List Scheduling Algorithms
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An Efficient List-Based Scheduling Algorithm for High-Level Synthesis
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
A heuristic scheduler for port-constrained floating-point pipelines
International Journal of Reconfigurable Computing
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This paper discusses design methodology of high-throughput arithmetic pipeline modules for an FPGA-based biochemical simulator. Since limitation of data-input bandwidth caused by port constraints often has a negative impact on pipeline scheduling results, we propose a priority assignment method of input data which enables efficient arithmetic pipeline scheduling under given input port constraints. Evaluation results with frequently used rate-law functions in biochemical models revealed that the proposed method achieved shorter latency compared to ASAP and ALAP scheduling with random input orders, reducing hardware costs by 17.57 % and by 27.43 % on average, respectively.