Computational frameworks for the fast Fourier transform
Computational frameworks for the fast Fourier transform
Energy-efficient signal processing using FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Multi-port interconnection networks for radix-R algorithms
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Fast and accurate resource estimation of automatically generated custom DFT IP cores
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Formal datapath representation and manipulation for implementing DSP transforms
Proceedings of the 45th annual Design Automation Conference
Mapping of Discrete Cosine Transforms onto Distributed Hardware Architectures
Journal of Signal Processing Systems
Permuting streaming data using RAMs
Journal of the ACM (JACM)
Low-complexity FFT/IFFT IP hardware macrocells for OFDM and MIMO-OFDM CMOS transceivers
Microprocessors & Microsystems
Accurate Area, Time and Power Models for FPGA-Based Implementations
Journal of Signal Processing Systems
Automatic IP generation of FFT/IFFT processors with word-length optimization for MIMO-OFDM systems
EURASIP Journal on Advances in Signal Processing - Special issue on quantization of VLSI digital signal processing systems
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This paper presents a parameterized soft core generator for the discrete Fourier transform (DFT). Reusable IPs of digital signal processing (DSP) kernels are important time-saving resources in DSP hardware development. Unfortunately, reusable IPs, however optimized, can introduce inefficiencies because they cannot fit the exact requirements of every application context. Given the well-understood and regular computation in DSP kernels, an automatic tool can generate high-quality ready-to-use IPs customized to user-specified cost/performance tradeoffs (beyond basic parameters such as input size and data format). The paper shows that the generated DFT cores can match closely the performance and cost of DFT cores from the Xilinx LogiCore library. Furthermore, the generator can yield DFT cores over a range of different performance/ cost tradeoff points that are not available from the library.