Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
A Methodology for Designing Optimal Self-Checking Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Self-Checking FSM Design with Observing only FSM Outputs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A Unified Scheme for Designing Testable State Machines
ATS '01 Proceedings of the 10th Asian Test Symposium
| Hi-index | 0.00 |
This paper presents a technique for designing self-checking finite state machines that uses a 2-hot code for state encoding. The registers and output logic in resulting state machines are testable online. A new method for designing the output logic is also proposed in this paper.