Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Reversible Computation in Asynchronous Cellular Automata
UMC '02 Proceedings of the Third International Conference on Unconventional Models of Computation
Building-Blocks for Designing DI Circuits
Building-Blocks for Designing DI Circuits
Iterative ring and power-aware design techniques for self-timed digital circuits
Iterative ring and power-aware design techniques for self-timed digital circuits
Embedding universal delay-insensitive circuits in asynchronous cellular spaces
Fundamenta Informaticae - Special issue on cellular automata
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Fault-tolerance in nanocomputers: a cellular array approach
IEEE Transactions on Nanotechnology
Discrete dynamical genetic programming in XCS
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
| Hi-index | 0.00 |
This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delay-insensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems. In the approach proposed in this paper the circuit expressions corresponding to a design are first converted into Reed---Muller forms and then implemented using delay-insensitive Reed---Muller cells. The design and layout of the Reed---Muller cell using primitives has been described in detail. The effects of stuck-at faults in both delay-insensitive primitives and gates have been analyzed. Since circuits implemented in Reed---Muller forms constructed by the Reed---Muller cells can be easily tested offline, the proposed approach for delay-insensitive circuit design improves a circuit's testability. Potential physical implementation of cellular arrays and its area overhead are also discussed.