Automatic Synthesis of Composable Sequential Quantum Boolean Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Journal of Electronic Testing: Theory and Applications
Reversible delay-insensitive distributed memory modules
RC'13 Proceedings of the 5th international conference on Reversible Computation
| Hi-index | 0.00 |
We show universality and minimality of sets of primitives, to construct delay-insentitive (DI) networks, which provide flexibility of their use in synthesis, and efficiency in their silicon implementation. Several approaches that improve on recent designs, in the literature, of a modulo-N counter are explored. Rudiments of a general design methodology for such asynchronous circuits via a few case-studies is provided. We obtain low constant latency, low constant response, constant power consumption and asymptotically optimal area-complexity for the counter. For moderately large N, the area complexity tends to match any possible design under synchronous (clocked) discipline and improves over existing delay-insensitive implementations. Additionally, an elegant mathematical analysis of this design problem gives a family of solutions to choose from. We also demonstrate the powerful property of timing-independent composability of DI circuits to obtain a very area-efficient modulo counter circuit. Finally, we find efficient DI decmpositions as well as transistor (switch-level) implementations of many important circuit modules, e.g., Join devices.