Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Testing of Digital Systems
Digital Fundamentals (9th Edition)
Digital Fundamentals (9th Edition)
Computer
ICC'09 Proceedings of the 13th WSEAS international conference on Circuits
Design register stack with bubble sorting function
EHAC'10 Proceedings of the 9th WSEAS international conference on Electronics, hardware, wireless and optical communications
| Hi-index | 0.00 |
The advances in VLSI technology have made possible many changes not only in the amount of hardware that can be integrated into a die permitting the implementation of single chip processor, but also in processor architecture. This creates a need for algorithms that can exploit a high degree of pipelining and parallelism. The algorithms that are the best at this time, for being able to incorporate a high degree of parallelism are the systolic arrays. The systolic systems have balanced uniform architectures which typically look like grids where each line indicates a communication path and each intersection represents a cell or a systolic element. Unfortunately as the scale of integration has increased so also has the occurrence of intermittent faults. The characteristics of these types of faults render them undetectable by standard test strategies. This is particularly problematic with the wide use of complex circuits in safety-critical applications. Ensuring the reliability of these systems is a major testing challenge. The detection of intermittent faults requires the use of Concurrent Error Detection (coding) techniques. This paper investigates the use of Berger code as a means of incorporating CED into a self checking systolic FIFO stack.