A Technique for Designing Totally Self-Checking Domino Logic Circuits

Authors:
C. K. Tang;P. K. Lala;J. P. Parkerson
Affiliations:
University of Arkansas, Fayetteville, AR;University of Arkansas, Fayetteville, AR;University of Arkansas, Fayetteville, AR
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

Citing 3
Cited 0

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Abstract

A scheme for concurrent self-checking domino logic circuit is proposed. The self-checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function. A checker circuit is embedded into the self-checking implementation. The scheme is especially suitable for large CMOS domino logic circuits.