A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Secure scan: a design-for-test architecture for crypto chips
Proceedings of the 42nd annual Design Automation Conference
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
S/390 parallel enterprise server CMOS cryptographic coprocessor
IBM Journal of Research and Development
Scan-based attack against elliptic curve cryptosystems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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In this paper, we presented a Design-for-Secure-Test (DFST) technique for pipelined AES to guarantee both the security and the test quality during testing. Unlike previous works, the proposed method can keep all the secrets inside and provide high test quality and fault diagnosis ability as well. Furthermore, the proposed DFST technique can significantly reduce test application time, test data volume, and test generation effort as additional benefits.