Authenticated-encryption with associated-data
Proceedings of the 9th ACM conference on Computer and communications security
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Efficient galois field arithmetic on SIMD architectures
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
Faster and Timing-Attack Resistant AES-GCM
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Cache attacks and countermeasures: the case of AES
CT-RSA'06 Proceedings of the 2006 The Cryptographers' Track at the RSA conference on Topics in Cryptology
Differential cache-collision timing attacks on AES with applications to embedded CPUs
CT-RSA'10 Proceedings of the 2010 international conference on Topics in Cryptology
Secure and fast implementations of two involution ciphers
NordSec'10 Proceedings of the 15th Nordic conference on Information Security Technology for Applications
CT-RSA'13 Proceedings of the 13th international conference on Topics in Cryptology
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We demonstrate new techniques to speed up the Rijndael (AES) block cipher using vector permute instructions. Because these techniques avoid data- and key-dependent branches and memory references, they are immune to known timing attacks. This is the first constant-time software implementation of AES which is efficient for sequential modes of operation. This work can be adapted to several other primitives using the AES S-box such as the stream cipher LEX, the block cipher Camellia and the hash function Fugue. We focus on Intel's SSSE3 and Motorola's Altivec, but our techniques can be adapted to other systems with vector permute instructions, such as the IBM Xenon and Cell processors, the ARM Cortex series and the forthcoming AMD "Bulldozer" core.