Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Simulation models for side-channel information leaks
Proceedings of the 42nd annual Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A Component-Based Design Environment for ESL Design
IEEE Design & Test
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips
IEEE Transactions on Dependable and Secure Computing
A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks
EUROCRYPT '09 Proceedings of the 28th Annual International Conference on Advances in Cryptology: the Theory and Applications of Cryptographic Techniques
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Early feedback on side-channel risks with accelerated toggle-counting
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
Automated Power Characterization for Run-Time Power Emulation of SoC Designs
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Power Analysis Attacks: Revealing the Secrets of Smart Cards
Power Analysis Attacks: Revealing the Secrets of Smart Cards
Hardware-Accelerated Workload Characterization for Power Modeling and Fault Injection
ATS '12 Proceedings of the 2012 IEEE 21st Asian Test Symposium
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System integration density increased tremendously in recent years, resulting in various problems for designers. First, a variety of dependability issues were a direct consequence from high clock frequencies and system-on-chip complexity, such as thermal, power, and stability challenges. Furthermore, deep sub-micron semiconductor processes were increasingly prone to single-event-upsets and multiple-event-upsets caused by logic degradation and environmental sources. Besides these reliability issues, the intentional introduction of faults into the system by adversaries, is of increasing concern to system developers of smart-cards. Therefore, there is a strong need for hardware-accelerated evaluation techniques during the design phase to identify weaknesses in cryptographic software implementations. To map power and fault models to such FPGA-based evaluation systems, characterization and benchmark approaches are described in literature, using general purpose benchmark software. Unfortunately, such non-specialized software can lead to various evaluation problems. Therefore, this paper proposes an hardware-accelerated methodology for the investigation of software implementations in the security and dependability domains. The applicability of the approach has been shown using a general available system-on-chip implementation.