Current flattening in software and hardware for security applications

Authors:
Radu Muresan;Catherine Gebotys
Affiliations:
University of Guelph, Guelph, Ontario, Canada;University of Waterloo, Waterloo, Ontario, Canada
Venue:
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Year:
2004

Citing 7
Cited 6

Power Analysis Attacks and Algorithmic Approaches to Their Countermeasures for Koblitz Curve Cryptosystems

IEEE Transactions on Computers
Non-deterministic Processors

ACISP '01 Proceedings of the 6th Australasian Conference on Information Security and Privacy
Statistics and Secret Leakage

FC '00 Proceedings of the 4th International Conference on Financial Cryptography
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems

CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Modeling and applications of current dynamics in a complex processor core

Modeling and applications of current dynamics in a complex processor core
Instantaneous current modeling in a complex VLIW processor core

ACM Transactions on Embedded Computing Systems (TECS)
Design principles for tamper-resistant smartcard processors

WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology

RIJID: random code injection to mask power analysis based side channel attacks

Proceedings of the 44th annual Design Automation Conference
A smart random code injection to mask power analysis based side channel attacks

CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
System level power profile analysis and optimization for smart cards and mobile devices

Proceedings of the 2008 ACM symposium on Applied computing
MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An automated framework for power-critical code region detection and power peak optimization of embedded software

PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Randomized Instruction Injection to Counter Power Analysis Attacks

ACM Transactions on Embedded Computing Systems (TECS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a new current flattening technique applicable in software and hardware. This technique is important in embedded cryptosystems since power analysis attacks (that make use of the current variation dependency on data and program) compromise the security of the system. The technique flattens the current internally by exploiting current consumption differences at the instruction level. Code transformations supporting current variation reductions due to program dependencies are presented. Also, a new real-time hardware architecture capable of reducing the current to data and program dependencies is proposed. Measured and simulated current waveforms of cryptographic software are presented in support of these techniques.