Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
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Power-Analysis Attack on an ASIC AES implementation
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
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Fudamentals of Digital Logic with VHDL Design
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On second-order differential power analysis
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
A digital design flow for secure integrated circuits
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Integrated Computer-Aided Engineering - Anniversary Volume: Celebrating 20 Years of Excellence
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Since the concept was publicly introduced, power analysis attacks on cryptographic systems have become an increasingly studied topic in the computer security community. Research into countermeasures for these cryptographic systems has been intensified as well. Experiments have been conducted to show the potential effectiveness of power analysis attacks and preventative techniques on both software (e.g. smartcard, DSP) and hardware (e.g. ASIC, FPGA) processing elements. One key observation that motivates our work is that the majority of the research into power analysis on FPGA-based cryptographic systems has been a) theoretical in nature, b) evaluated through simulation, or c) experimented using custom hardware that does not closely mirror real-world systems. In this paper, we look to bridging this gap between theory and practice by detailing our experience in performing a Differential Power Analysis (DPA) attack on a commercial FPGA development board. We present an automated data acquisition and analysis design for an FPGA-based implementation of the Data Encryption Standard (DES). Based on our experience with this attack automation system, we provide an analysis of the features that exist in most commercial FPGA boards which can prevent an effective DPA attack.