A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard

Authors:
G. Natale;M. Doulcier;M. L. Flottes;B. Rouzeyre
Affiliations:
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS UMR 5506, Montpellier Cedex 5, France 34392;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS UMR 5506, Montpellier Cedex 5, France 34392;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS UMR 5506, Montpellier Cedex 5, France 34392;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS UMR 5506, Montpellier Cedex 5, France 34392
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2009

Citing 6
Cited 1

Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard

IEEE Transactions on Computers
Empirical evidence concerning AES

ACM Transactions on Modeling and Computer Simulation (TOMACS)
Low Cost Concurrent Error Detection for the Advanced Encryption Standard

ITC '04 Proceedings of the International Test Conference on International Test Conference
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard

IEEE Transactions on Computers
An On-Line Fault Detection Scheme for SBoxes in Secure Circuits

IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A compact AES core with on-line error-detection for FPGA applications with modest hardware resources

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an on-line self-test architecture for hardware implementation of the Advanced Encryption Standard (AES). The solution exploits the inherent spatial replications of a parallel architecture for implementing functional redundancy at low cost. We show that the solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, the architectural modification for on-line test does not weaken the device with respect to side-channel attacks based on power analysis.