Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
On-Line Testing Scheme for Clock's Faults
Proceedings of the IEEE International Test Conference
Proceedings of the IEEE International Test Conference 2001
Proceedings of the 40th annual Design Automation Conference
A Structural Test Methodology for SRAM-Based FPGAs
Proceedings of the 15th symposium on Integrated circuits and systems design
Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
An asynchronous totally self-checking two-rail code error indicator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
An Integrated Design Approach for Self-Checking FPGAs
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Design for Testability of FPGA Blocks
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
New ECC for Crosstalk Impact Minimization
IEEE Design & Test
Low Cost Concurrent Error Detection for the Advanced Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
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In this paper we present a novel circuit for the on-line detection of transient and crosstalk faults affecting the interconnects of systems implemented using Field Programmable Gate-Arrays (FPGAs). The proposed detector features self-checking ability with respect to faults possibly affecting itself, thus being suitable for systems with high reliability requirements, like those for space applications. Compared to alternate solutions, the proposed circuit requires a significantly lower area overhead, while implying a comparable, or lower, impact on system performance. We have verified our circuit operation and self-checking ability by means of post-layout simulations.