Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Crafting a compiler
A case for redundant arrays of inexpensive disks (RAID)
SIGMOD '88 Proceedings of the 1988 ACM SIGMOD international conference on Management of data
A scheduling and resource allocation algorithm for hierarchical signal flow graphs
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Automated micro-roll-back self-recovery synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Transformation-based high-level synthesis of fault-tolerant ASICs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Wafer-Scale Integration of Systolic Arrays
IEEE Transactions on Computers
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays
IEEE Transactions on Computers
Proceedings of the 38th annual Design Automation Conference
Efficient Self-Recovering ASIC Design
IEEE Design & Test
Intellectual Property Metering
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Synthesis of application-specific highly efficient multi-mode cores for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Highly flexible multi-mode system synthesis
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An error recoverable structure based on complementary logic and alternating-retry
Journal of Computer Science and Technology
EURASIP Journal on Applied Signal Processing
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In this paper, behavioral-level synthesis techniques are presented for the design of reconfigurable hardware. The techniques are applicable for synthesis of several classes of designs, including 1) design for fault tolerance against permanent faults, 2) design for improved manufacturability, and 3) design of application specific programmable processors (ASPP's)--processors designed to perform any computation from a specified set on a single implementation platform. This paper focuses on design techniques for efficient built-in self-repair (BISR), and thus directly addresses the former two applications. Previous BISR techniques have been based on replacing a failed module with a backup of the same type. We present new heterogeneous BISR methodologies which remove this constraint and enable replacement of a module with a spare of a different type. The approach is based on the flexibility of behavioral-level synthesis to explore the design space. Two behavioral synthesis techniques are developed; the first method is through assignment and scheduling, and the second utilizes transformations. Experimental results verify the effectiveness of the approaches.