A multicycle communication architecture and synthesis flow for global interconnect resource sharing

Authors:
Wei-Sheng Huang;Yu-Ru Hong;Juinn-Dar Huang;Ya-Shih Huang
Affiliations:
National Chiao Tung University, Hsinchu, Taiwan;National Chiao Tung University, Hsinchu, Taiwan;National Chiao Tung University, Hsinchu, Taiwan;National Chiao Tung University, Hsinchu, Taiwan
Venue:
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Year:
2008

Citing 5
Cited 2

MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
High-level synthesis under multi-cycle interconnect delay

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Behavior-to-placed RTL synthesis with performance-driven placement

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Architecture-level synthesis for automatic interconnect pipelining

Proceedings of the 41st annual Design Automation Conference
Architecture and synthesis for on-chip multicycle communication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distributed register (DR) architecture to cope with this increasing latency. The DR architecture, though allows multicycle communication, introduces extra overhead on interconnect resource. In this paper, we propose the Regular Distributed Register - Global Resource Sharing (RDR-GRS) architecture to enable global sharing of interconnects and registers. Based on the RDR-GRS architecture, we further define the channel and register allocation problem as a path scheduling problem of data transfers. A formal and flexible formulation of this problem is then presented and optimally solved by Integer Linear Programming (ILP). Experimental results show that RDR-GRS/ILP can averagely reduce 58% wires and 35% registers compared to the previous work.