Multiple-Way Network Partitioning
IEEE Transactions on Computers
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Generalization of Min-Cut Partitioning to Tree Structures and its Applications
IEEE Transactions on Computers
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
| Hi-index | 14.98 |
We consider two generalizations of the min-cut partitioning problem where the nodes of a circuit C are to be mapped to the vertices of an underlying graph G, and the cost function to be minimized is the cost of associating the nets of C with the edges of G. Let P be the number of pins, t be the number of nodes of G, and d be the maximum number of cells on a net of C. In the first problem the graph G is a tree T. An iterative improvement heuristic is given in [9] with O(P·t3) time per pass. Our proposed heuristic guarantees identical solutions in O(P·t· min{d, t}) time per pass. The second problem is defined on any graph G. The standard iterative improvement heuristic requires O(P·t4) time per pass, but our proposed approach guarantees O(P·t· min{d, t}) time per pass. The problems find applications in VLSI physical design and in distributed systems.