Computational geometry: an introduction
Computational geometry: an introduction
Robust FPGA intellectual property protection through multiple small watermarks
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Hierarchical composition of vlsi circuits
Hierarchical composition of vlsi circuits
Publicly detectable techniques for the protection virtual components
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Intellectual Property Metering
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
A SVD-based fragile watermarking scheme for image authentication
IWDW'02 Proceedings of the 1st international conference on Digital watermarking
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This paper addresses the copyright protection problem of integrated circuits designed with blocks which are originated from multiple design sources. The process consists of two phases. First, a compact signature is generated from every block independently and made public. Utilizing such signatures, a design can be decomposed into its original building blocks, regardless of multiple hierarchies. Then, a map of all the blocks can be built, thus allowing to reconstruct the original copyright dependencies. The proposed methodology can be used by foundries to verify that designs submitted for fabrication contain blocks traceable to a legal source of intellectual property. The verification process is also useful to intellectual property providers and integrators, as it reduces the likelihood of infringement, thus ultimately minimizing the risk of litigation.