A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs

Authors:
M. Favalli;B. Ricco;L. Penza
Affiliations:
D.E.I.S., University of Bologna, Viale Risorgimento 2, 40136 Bologna, Italy;D.E.I.S., University of Bologna, Viale Risorgimento 2, 40136 Bologna, Italy;SGS-Thomson Microelectronics, Via C. Olivetti, 2 - Agrate Brianza - Italy
Venue:
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Year:
1995

Citing 0
Cited 1

On the design of self-checking functional units based on Shannon circuits

DATE '99 Proceedings of the conference on Design, automation and test in Europe

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Abstract

This paper presents a technique for on-chip detection of (resistive) Bridging Faults (BFs) in CMOS (and BiCMOS) circuits, that improves the state of the art of testing in the following aspects: 1) compared with off-chip I/sub DDQ/ testing, it is much faster; 2) compared with on-chip Built-In Current Sensors (BICS), it avoids the use of extra devices in series with the functional circuits; 3) compared with both techniques, it is inherently selective, because it detects only BFs producing extra delays in excess of specified maximum values; 4) it can be used for on-line testing. The method of this work must be applied in addition to functional testing, that takes care of stuck-at and equivalent faults. In the case of buffers, our approach can be slightly modified to also detect stuck-at faults.