Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks

Authors:
Andrzej Krasniewski
Affiliations:
Warsaw University of Technology
Venue:
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Year:
2004

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Abstract

We propose a low-overhead concurrent error detectionscheme for a sequential circuit implemented using anFPGA with embedded memory blocks (EMBs). Thepresented scheme is proven to detect each permanent ortransient fault associated with a single input or output ofany component of the circuit that leads to an incorrect statetransition. Such faults are detected with no latency. Ourtechnique requires significantly less extra logic than theearlier proposed schemes for concurrent error detection insequential circuits. For a large percentage of the examinedbenchmark circuits, no extra EMBs and just 3 extra LUTsare needed; for other circuits, the number of extra EMBs isquite limited - on average, an overhead in terms of thenumber of EMBs is 13.6%.