SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Technology mapping for FPGAs with embedded memory blocks
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Technology mapping for large complex PLDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid product term and LUT based architectures using embedded memory blocks
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Technology mapping for k/m-macrocell based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Area-Optimized Technology Mapping for Hybrid FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
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We examine ways to increase product term usage efficiency and propose several new sharing architectures that addresses this problem. We also present a technology mapping algorithm for product term based FPGA embedded memory arrays. Our algorithm, pMapster, is used to investigate the effects of macrocell granularity and macrocell sharing on the amount of logic that can be packed into a product term embedded memory array