On nominal delay minimization in LUT-based FPGA technology mapping

Authors:
Jason Cong;Yuzheng Ding
Affiliations:
UCLA Computer Science Department, Los Angeles, CA;UCLA Computer Science Department, Los Angeles, CA
Venue:
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Year:
1995

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Abstract

We study the nominal delay minimization problem in LUT-based FPGA technology mapping, where interconnect delay is assumed proportional to net fannout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K≥3, and remains NP-hard for duplication-free mapping and tree-based mapping for K≥5 (but is polynomial time solvable for K = 2). We also present a simple heuristic to take nominal delay into consideration during LUT mapping for delay minimization.