Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Logic for applications
Algorithms for solving Boolean satisfiability in combinational circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Simplification: A General Constraint Propagation Technique for Propositional and Modal Tableaux
TABLEAUX '98 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
The Industrial Success of Verification Tools Based on Stålmarck's Method
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Applying GSAT to non-clausal formulas
Journal of Artificial Intelligence Research
Pushing the envelope: planning, propositional logic, and stochastic search
AAAI'96 Proceedings of the thirteenth national conference on Artificial intelligence - Volume 2
Justification-Based Local Search with Adaptive Noise Strategies
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
Tableau calculi for answer set programming
ICLP'06 Proceedings of the 22nd international conference on Logic Programming
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Boolean circuits offer a natural, structured, and compact representation of Boolean functions for many application domains. In this paper a tableau method for solving satisfiability problems for Boolean circuits is devised. The method employs a direct cut rule combined with deterministic deduction rules. Simplification rules for circuits and a search heuristic attempting to minimize the search space are developed. Experiments in symbolic model checking domain indicate that the method is competitive against state-of-the-art satisfiability checking techniques and a promising basis for further work.