The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Machine-Oriented Logic Based on the Resolution Principle
Journal of the ACM (JACM)
The SLAM project: debugging system software via static analysis
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
Symbolic Model Checking
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
A Validation Technique for Tightly Coupled Protocols
IEEE Transactions on Computers
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Finite automata and their decision problems
IBM Journal of Research and Development
General technique for communications protocol validation
IBM Journal of Research and Development
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Interpolant-based transition relation approximation
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
25 Years of Model Checking
Making software verification tools really work
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
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In the last quarter century computer-aided verification --- especially in the form of model checking --- has evolved from a research concept to a commercial product. While the pace of this technology transfer was anything but rapid, the new technology had almost insuperable hurdles to jump on its way to the market place. Hurdle number one was a required significant change in methodology. On account of its limited capacity, model checking must be applied only to design components (RTL blocks in the case of hardware) instead of the whole design as with simulation test. Thus, the functional behavior of these design components must be specified. Since component level functionality is often revealed at best obscurely in the design's functional specification, either designers must convey component functionality to those doing the testing or else testers must somehow fathom it on their own. The former was considered an unacceptable diversion of vaunted designer resources while the latter was often undoable. A second hurdle was uncertainty surrounding the quality of the new tools. Initially the tools were incomparable and required the user to create considerable tool-specific infrastructure to specify properties before a tool could be evaluated. Recreating the required infrastructure for several tools was infeasible. This meant choosing a tool without a head-to-head evaluation against other tools. With the high cost and uncertain outcome afforded by these hurdles, no circuit manufacturer was willing even to consider seriously this new technology. Not, that is, until the cost of testing-as-usual became higher than the cost of jumping these formidable hurdles. This essay is the saga of the transfer of computer-aided verification technology from research to the market place.