Analysis of Timed Systems Using Time-Abstracting Bisimulations
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Bounded Model Checking for the Existential Fragment of TCTL$_{-G}$ and Diagonal Timed Automata
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Reachability Analysis for Timed Automata Using Partitioning Algorithms
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This paper presents an on-the-fly and symbolic algorithm for checking whether a timed automaton satisfies a formula of a timed temporal logic which is more expressive than TCTL. The algorithm is on-the-fly in the sense that the state-space is generated dynamically and only the minimal amount of information required by the verification procedure is stored in memory. The algorithm is symbolic in the sense that it manipulates sets of states, instead of states, which are represented as boolean combinations of linear inequalities of clocks. We show how a prototype implementation of our algorithm has improved the performances of the tool KRONOS for the verification of the FDDI protocol.